Wednesday, June 22, 2016

Prj 146 - Dual Channel 40MSPS ADC (Part1)

With the F board (BeagleBone Black Spartan6 LX9 FPGA), I now have the option of using both faster ADCs as well as dual channel variants to support quadrature down converters.  This board uses a LTC2292 which is a dual channel 40MSPS 12 bit ADC.  It is similar to previous LTC ADCs I have used (FPGA variant and non-FPGA).  The schematic of the board is shown below.
Dual ADC Schematic - LTC2292, IF inputs, and sample clock.
Dual ADC Schematic - Voltage Regulators
There are a couple of variants and decisions on the board worth noting.  First, I configured it to use 0.5V full scale rather than 1V and configured the output to be signed 12 bit values.  Second, the analog inputs are similar to previous versions using a center tap transformer with 50 ohm input termination. This comes directly from the manufacture reference design and has worked well in the past.  Finally, a 40MHz CMOS oscillator is used but with a buffer to the FPGA on the carrier board. Separate regulators are used for the analog and digital supply voltages.  Everything is 3.3V and liberally supplied with bypass capacitors and chokes. The Kicad source material for the the board is available on github here. The board is a two layer OSHPark with the layout shown below.
Dual ADC Two Layer PCB Layout
A picture of the first unit assembled and mounted on an F board (mounted on a BBB) is shown below.
Dual 40MSPS ADC board.  Connectors at right are from the underlying F board it is mounted on.  Connectors on the left are from the underlying Beagle Bone Black which the F board is mounted on.
For testing purposes the anti-aliasing low pass filter elements were not populated.  This board is designed to work with a digital down converter VHDL image on a Spartan 6 LX9 (F board).  The construction of this board is straightforward.  The only difference is that with this unit I tried applying solder paste using 22gauge plastic needle with paste syringe.  In previous work I only had the default metal large needle that comes with the paste syringe itself.  Using the fine plastic needles make a huge difference, you can dispense fine amounts of paste and let the needle touch the pads without fear of the metal scraping.

Prj 145 - Beagle Bone Black Simple LX9 FPGA board (Part 1)
Prj 145 - BBB LX9 FPGA Board Design (Part 2)
Prj 145 - BBB LX9 FPGA Board Construction (Part 3)
Prj 145 - BBB LX9 JTAG Boundary Scan Utilities (Part 4)
Prj 145 - BBB LX9 C++ and VHDL (Part5)

Thursday, June 2, 2016

Prj 144 - DVB Tuner Board

I wanted to use one of the existing DVB tuners for various RF applications.  The appeal of these ICs is that they include a high level of integration with quadrature mixers, amplifiers and filters, are cheap and easily accessible, come in small packages, and are relatively easy to use.

I finalized on the MAX2112.  Based on experience with other devices with high levels of integration I decided to start simple and build a small board based on the circuit in the manufacturer evaluation board (I would have just used their eval board, however, these are always incredibly expensive).  The following circuit captures that board.
DVB Tuner Board Schematic
Two separate low noise regulators are provided although one is sufficient given the low power of the device.  The MAX2112 has a 75 ohm input impedance so provisions are made for a resistive broadband input match (and associated loss of input power) or a LC tuned input match to bring the board input impedance to 50 ohms.  The loop filter for the synthesizer was copied from evaluation circuit without modification.  The differential outputs were converted to single ended using op-amps.  The only change from the evaluation board is the inclusion of a DAC to provide a programmable voltage to the AGC input of the device.  The DAC was selected to have an I2C address different from the tuner.

Since this was my first part using an I2C interface it took some time to develop and debug the software (Tboard and user space I2C).  The board was populated with only the I2C DAC and an LED on its output.  Normally adding an LED is not good practice as it can add noise (something not desirable on the input voltage to a high gain AGC amplifier), however, for testing purposes it proved very helpful. Initial development and testing was conducted using an I board and then updated to support an Fboard with BDC VHDL.  The first unit used a 20MHz crystal, while the loop filter values were specified for a 27MHz crystal from the evaluation board.  This worked out ok since via software control I was able to divide the reference oscillator by 2 and achieve lock.  Below is a picture of that unit.
MAX2112 Based Tuner Board (second regulator not populated)
The programming information is a little sparse.  If you have used a synthesizer before it makes sense but I would not choose this as the first part to work with a PLL (loop filter, lock debug).  The one subtlety was the initial value of the VCO filter registers.  If you change these from the power on default I had problems with the device locking.  It seems to conduct the VCO search in only one direction in frequency (this wasn’t entirely clear from the data sheet or reference board material).  Having overcome this, I was able to test both IF channels using RF inputs across the fully specified range.

There are all kinds of characterizations I wanted to perform but without much test equipment and particularly equipment setup for quadrature baseband evaluation, I decided to keep it simple and move on to a dual channel ADC I could use with this board.  A quick check of the input amplifier gain showed reasonable and expected performance.  The other quick test easily accomplished was checking the programmable filter response.  The simplest, albeit not quite so accurate, was to set a tuning value and filter cut off frequency and scan a RF tone about the tuning frequency.  I could then use a spectrum analyzer with max hold history on and get the outer envelope of the fundamental as it was sweep through the frequency range.  The following diagram captures those results.

Programmable Filter Response (See text for measurement approach and caveats)
The down side with this approach is that the second harmonic of the spectrum analyzer is higher than the filter roll off very far into the stop band.  What this translates into is frequencies far away from the pass band end up seeing a higher max hold value than actual due to the second harmonic pushing up the history value.  So basically once you get -30dB or more down in the response you cannot see the true roll off of the filter, rather something less which is pushed up due to harmonics in the measurement device when it is seeing the fundamental at lower frequencies.  The tuner is set to 975MHz with the input swept from this to +20MHz.  An attenuator is used at the analyzer input to keep the signal level low to minimize its harmonic responses.  The analyzer is a 50 ohm input on a single output IF channel with the other terminated in 50 ohms.

So in short, the tuner is working as expected and within my current measurement capabilities.  Further characterization will have to wait until I have a dual channel ADC.