|10MSPS ADC Cape for Beaglebone Black|
The clock circuitry is immediately below this. A simple CMOS TCXO is used, however, provisions are made for a divide by two configuration. The land is chosen for a FOX924B. This part has worked well for me in the past and is widely available in frequencies from 10MHz to 27MHz. While the ADC is capable of 10MSPS the divide by two allows for various sample clock frequencies to be used. For example a 19.44MHz TCXO can be used with a divide by 2 to produce a sample clock of 9.72MHz. This sample frequency has the advantage that is shifts the location of 10.7MHz closer to the center of a Nyquist band than just using a 10.0MHz sample clock.
The LTC2225 in the lower left connects to 12 bits on the PRU1 input register. In addition, the sample clock is present as an input. This allows the PRU to wait for a sample clock transition and then read the ADC value. The ADC is strapped to produced unsigned integer values and the range is set for 1V. The common output voltage is bypassed with a capacitor and provided to the buffer amplifier.
Immediately above the ADC in the schematic is a filter network between the buffer amplifier and the ADC. This can be populated in a variety of configurations from a 3rd order bandpass filter to a simple first order low pass filter. In its simplest configuration all of the series elements are 0 ohm pass throughs and none of the shunt elements are populated except C115 (75pF). This configuration provides a first order 21MHz low pass filter (the 3dB point is chosen to be at the second harmonic).
The LTC6404 is in the upper left and provides buffering, amplification, and single ended to balanced conversion. The QFN version of the device is used so there are integrated 50 ohm resistors in line with each output. These work with the filter network following it. The LTC6406 provides both single ended to balanced conversion and some gain. Using a fully differential amplifier (FDA) has some of subtleties. There are good application notes on FDAs from both TI and ADI. The resistor values are correct as it is designed to be a 50 ohm input with a 50 ohm source. The 25 ohm resistor R102 appears as roughly 50 ohms input impedance with the feedback network of the FDA. The other side input of the FDA output sees both the 25 ohm gain resistor plus 50 ohms to balance out the source impedance, thus producing 75 ohms and balancing both sides of the amplifier.
The io pins are chosen to allow an interface board to be stacked on top without interfering. This allows a couple of ports of SPI/GPIO and power to 3 other boards from the same BBB hosting the ADC. The ground plane is separated into a digital and analog plane with the analog plane surrounding the buffer amplifier, filter, and ADC input. This plane is tied to the rest of ground at a single point through ferrite chokes. The 3.3V supply is also separated into an analog and digital portion via a choke. A view of the PCB is at the end of the BREC2 Gallery. The sample clock runs are not as nice as I would like but there is only so much you can do with two layers.
A picture of the first unit is below.
|10MSPS ADC on a Beaglebone Black. TCXO in upper left, LTC2225 in upper right, power on reset and regulators lower left and LTC6406 in lower right.|