Sunday, March 29, 2015

Prj137 10MSPS ADC

A couple of updates to the ADC board were made.  These included corrections to the power on reset circuitry and the addition of 0805 pads for a band pass filter between the buffer and the ADC.  The schematic is below.
10MSPS ADC Cape for Beaglebone Black
Walking through the schematic, the regulator and power on reset circuitry are in the upper right. A low noise regulator is used to provide 3.3V within the board.  The output enable of the ADC is generated by and'ing together the BBB system reset line with a gpio line.  The gpio used was selected as it powers up low and must be explicitly set high.  The outputs of the ADC must remain in a high Z state as they are on the boot config pins of the BBB.  If you don't do this, they are loaded by the ADC and the unit does not boot correctly.

The clock circuitry is immediately below this.  A simple CMOS TCXO is used, however, provisions are made for a divide by two configuration.  The land is chosen for a FOX924B.  This part has worked well for me in the past and is widely available in frequencies from 10MHz to 27MHz.  While the ADC is capable of 10MSPS the divide by two allows for various sample clock frequencies to be used.  For example a 19.44MHz TCXO can be used with a divide by 2 to produce a sample clock of 9.72MHz.  This sample frequency has the advantage that is shifts the location of 10.7MHz closer to the center of a Nyquist band than just using a 10.0MHz sample clock.

The LTC2225 in the lower left connects to 12 bits on the PRU1 input register.  In addition, the sample clock is present as an input.  This allows the PRU to wait for a sample clock transition and then read the ADC value.  The ADC is strapped to produced unsigned integer values and the range is set for 1V.  The common output voltage is bypassed with a capacitor and provided to the buffer amplifier.

Immediately above the ADC in the schematic is a filter network between the buffer amplifier and the ADC.  This can be populated in a variety of configurations from a 3rd order bandpass filter to a simple first order low pass filter.  In its simplest configuration all of the series elements are 0 ohm pass throughs and none of the shunt elements are populated except C115 (75pF).  This configuration provides a first order 21MHz low pass filter (the 3dB point is chosen to be at the second harmonic).

The LTC6404 is in the upper left and provides buffering, amplification, and single ended to balanced conversion.  The QFN version of the device is used so there are integrated 50 ohm resistors in line with each output.  These work with the filter network following it.  The LTC6406 provides both single ended to balanced conversion and some gain.  Using a fully differential amplifier (FDA) has some of subtleties. There are good application notes on FDAs from both TI and ADI.  The resistor values are correct as it is designed to be a 50 ohm input with a 50 ohm source.  The 25 ohm resistor R102 appears as roughly 50 ohms input impedance with the feedback network of the FDA.  The other side input of the FDA output sees both the 25 ohm gain resistor plus 50 ohms to balance out the source impedance, thus producing 75 ohms and balancing both sides of the amplifier.

The io pins are chosen to allow an interface board to be stacked on top without interfering.  This allows a couple of ports of SPI/GPIO and power to 3 other boards from the same BBB hosting the ADC.  The ground plane is separated into a digital and analog plane with the analog plane surrounding the buffer amplifier, filter, and ADC input.  This plane is tied to the rest of ground at a single point through ferrite chokes.  The 3.3V supply is also separated into an analog and digital portion via a choke.  A view of the PCB is at the end of the BREC2 Gallery. The sample clock runs are not as nice as I would like but there is only so much you can do with two layers.

A picture of the first unit is below.
10MSPS ADC on a Beaglebone Black.  TCXO in upper left, LTC2225 in upper right, power on reset and regulators lower left and LTC6406 in lower right.
This approach is still low cost and can be easily constructed by hand. The populated board is roughly $45 (LTC6406 $7, LTC2225 $10 FOX924 $3 ADP150 $1 - all quantity 1 from Digikey, connectors $5 from Adafruit, SMA $1 from eBay quantity 25 and PCB $11 quantity 3 from OSHPark).

Saturday, March 21, 2015

Level Controlled RF CW Synthesizer

Using an amplifier, attenuator, splitter and power detector (Prj135) along with an older project with an ADF4351 synthesizer (Prj131 - a variant of Prj133 without the mixer), a Beagle Bone Black, and a SPI interface (Prj130), a controlled level RF CW synthesizer configuration was created.  Without some kind of feedback a standalone signal source is susceptible to level variance, particularly with load reactance and interaction with cable length - an example is here.  By measuring and attenuating you get an AGC loop to set the level.  A block diagram of the setup is below.
Block Diagram of Constant Level Synthesizer Setup using a Beaglebone Black.
A picture of the physical setup is below.
Level Controlled Synthesizer Setup.  Beaglebone Black at left with interface board, synthesizer in upper center, and level control board on right.
The synthesizer has a coarse level control (3 steps of approximately 3dBm).  The digital step attenuator provides 30dBm of attenuation while the amplifier +20dB of gain up to +8dBm through 2700MHz. Software on the Beagle Bone Black sets the synthesizer at its lowest output level at the desired frequency along with maximum attenuation at the digital attenuator.  The power at the detector is measured (multiple samples averaged over 5mS) and compared to the desired level.  The attenuation is reduced by half the delta until the detector reading is within 0.25dBm of the target or until the attenuation setting is 0dB.  If the level cannot be achieved, the synthesizer output level is increased one step and the entire process is repeated.  The following diagram captures measured outputs at various levels and with different measurement devices.
Level Controlled Synthesizer 0.040 - 2 GHz Results
All devices show are +/-2dB. The 0dBm output at 1900MHz shows a sag where the synthesizer output has dropped enough with frequency that the amplifier cannot bring it quite to 0dBm.  You can see the SA0314 has a couple of small spikes in response around 500MHz and 1100MHz. You can also see the 7L12 agrees quite well until about 1500MHz (the traces stop at 1800MHz as this is its limit).

Saturday, March 7, 2015

Prj135 RF RMS Power Meter (Part3)

I decided to construct the second level control board using a power divider rather than sampling network to the RMS power detector as in the previous post.  Using a sampling resistor loads the output less but is susceptible to errors based on the load impedance variance. There is a choice between using a two resistor and three resistor configuration.  A detailed treatment of why a 2R divider works better than a 3R divider for level ratio applications is well described in “Choosing the Right Power Splitter: Two-resistor or Three-resistor; B. R. Smith, National Conference of Standards” (Currently available from the Keysight website).  The modifications to the original circuit are shown below.
2R 6dB Power Splitter with Matching Network for LTC5587
A picture of the end result is shown below.  You can see the stacked capacitor over the underlying cut trace between the 50 ohm resistor and the SMA post.  In the lower right you can see the matching network to the power meter.
Unit #2 using a 2R divider (upper right between U103 and SMA) and 50 ohm matching network at meter (lower right to the right of the LTC5587 at U105).
The mV/dBm response of the meter was measured using the same techniques described in the previous post. The following graph shows scans for the sub 1GHz region.
Power Meter Response 40MHz - 1000MHz.
The results are amazingly good and near Y [dBm] = (M=32.5 mV/dBm) * mV + (B=-43 dBm). The measurement error of the instrumentation equipment and setup is at least +/- 2 dBm.  The following is the same data over the 1GHz - 2GHz region.
Power Meter Response 1000MHz - 2000MHz
The results in this band are floating a bit high compared with the previous band but still within measurement error and device specification.  The following captures the response in the 2GHz - 3GHz region.
Power Meter Response 2000MHz - 3000MHz
Again, the results are bit higher than the 1GHz band but within expected results.  The amplifier is only stated to 2700MHz so you see the level reduction starting here.

The slope and intercept are both a little higher than the nominal value from the datasheet.  They actually look closer to some of the higher temperature data listed.  My guess is I didn't get the QFN paddle soldered sufficiently well to make a good thermal junction and the part is running warm.

A couple of different 50 ohm matching configurations were tried. No matching (device direct) worked well in the sub 1GHz region and increased sensitivity, however, above this the results were not usable.  A 2.2nH serial inductor with no shunt capacitor was tried.  This produced good results through 2GHz (not much difference than the above except the >1900MHz results were closer to the B=-43dBm line).